This invention is generally directed to MOS (metal oxide semiconductor) clock generators. It is particularly directed to an improved trigger circuit for use with such clock generators.
MOS memories invariably include one or more clock generators which are used to control various internal memory functions. Typically, each clock generator includes a bootstrap circuit to develop a high level clock output signal, and a pre-charge and trigger circuit to condition the bootstrap circuit for proper firing. U.S. Pat. No. 4,061,933 discloses a clock generator of this type.
Such conventional clock generators suffer from a number of problems. Their relatively high power dissipation and their relatively low gain (due to high input capacitance) are but two of their drawbacks. In addition, their clock output voltages frequently are multi-sloped. Consequently, the circuitry driven by these clock outputs must be specially designed to accommodate these characteristics.
Another problem frequently associated with conventional clock generators is that the delay associated with their outputs cannot be easily varied. Moreover, as temperature and other variables change, their delay does not track well with corresponding changes in the circuitry driven by the clock outputs.
Yet another problem with some prior clock generators is that their front end trigger circuits cannot perform logic functions (ANDing, ORing, etc.) to develop a logic controlled output without paying the penalty of increased power dissipation. The present invention overcomes this problem and the other problems mentioned above by providing an improved trigger circuit for a clock generator.